Summary

My research focuses on the co-design of algorithms and specialized hardware for localization, mapping and path-planning on energy-efficient miniature robots. I enjoy working in a collaborative, multidisciplinary environment for both academic research and industry projects that have positive impacts on our society and environment.

Research Interests

  • Energy-efficient High-performance Architectures
  • Hardware-friendly Algorithms
  • Hardware-accelerated Machine Learning
  • Analog Mixed-Signal IC Design

Research Projects

Graduate Research Projects

  • High-throughput Computation of Shannon Mutual Information on Chip

    This is a multi-core accelerator for computing fast Shannon mutual information that facilitates efficient autonomous exploration (completed in Jan. 2019 in collaboration with Zhengdong Zhang)

    Robotic exploration problems arise in various contexts, ranging from search and rescue missions to underwater and space exploration. In these domains and beyond, exploration algorithms that can rapidly reduce uncertainty can provide significant benefits, for instance, by shortening time and reducing resources required for exploration. Unfortunately, principled algorithms based on rigorous information-theoretic metrics, such as, maximizing Shannon mutual information along the exploration path, are computationally extremely demanding.

    In this project, I proposed a novel multi-core accelerator that computes Shannon mutual information for the entire occupancy grid map in real-time and illustrated that the throughput of the such hardware is dictated by its memory architecture and data delivery method. In other words, I found that parallelization alone is not sufficient for high-throughput computation. In addition, it is critical to consider (i) memory management, e.g., how data is placed and organized in memory, (ii) data delivery, e.g., how data is accessed and delivered to parallel cores, so that throughput scales well with increasing parallelization.

    We argue that the effective co-design of computing hardware and algorithms for robotics applications will be enabled by novel methods in data flow on chip, for instance, rather than counting the number of operations or amount of memory required that has been essential to developing robotics algorithms for CPUs.

Undergraduate Research Projects

  • Implantable Bio-sensing & Impedance Imager

    Collaborated with an IC graduate student to design the schematic and layout design of this imager, which is used for impedance sensing of ion concentrations inside the brain (Sept. 2017 - Present)

    This was my Bachelor’s thesis project with the Intelligent Sensory Microsystems Laboratory at the University of Toronto.

    This imager was an implantable IC that can measure the impedance of the brain tissue for ion-concentration sensing purposes. It contained 32 x 32 delta-sigma based impedance sensing channels with a large coil for inductive power and data transfer. The chip was taped out using the IBM 0.13um technology. During this project, I enhanced the schematic design and produced the layout for the entire imager to satisfy several performance specifications and power constraints. This chip is currently being manufactured and will be tested in early 2018.

  • Evaluation of the Effectiveness of TSMC 16nm FinFETs in ADC Design

    Designed a current-steering DAC using transistors in the TSMC 16nm FinFET Technology (completed in the summer of 2017)

    This project was completed under the supervision of Hajime Shibata, a senior analog IC designer at Analog Devices Inc. (ADI) in the Toronto Design Centre. The project was a part of my 16-month internship with ADI from May 2016 – Aug. 2017. 

    Analog Devices Inc. had initiated migration to the TSMC 16nm FinFET technology from TSMC 28nm technology at the time of my internship.  At the beginning stage of the migration, design / simulation tools, design methodologies, and manufactured silicon components in this new technology needed to be tested via designing a test-chip. This test-chip consisted of a 2-stage ADC with various supporting digital blocks. I was responsible for the design, simulation, and layout of the thermometer-coded current steering DAC in this test-chip. Challenges and their solutions encountered during my design process were shared globally across many ADI design centres to facilitate the migration process.

  • Image Scene Prediction using Machine Learning Techniques

    Designed and trained a Convolutional Neural Network (CNN) to successfully classify images into 8 categories (completed during the fall of 2016)

    This project was completed as a part of the final evaluation of CSC411, a graduate-level machine learning course offered in the 2016 fall semester at the University of Toronto. 

    This project required the investigation of several machine learning algorithms to classify 128 x 128 color JPG images into 8 categories {1 –structure, 2 –indoor, 3 –people, 4 –animals, 5 –plant life, 6 –food, 7 –cars, 8 -sea}. There are 7000 training images with labels, 970 public test images, and 2000 private test images. The final score was based on the classification accuracy of the 2970 test images.

    After comparing the accuracy of several machine learning techniques, CNN is determined to the best for classifying images. For a CNN with 2 convolutional and 2 fully connected layers, the accuracy of such classifier is 55%, which beats the accuracy instructor-trained CNN (49% accuracy). To improve the performance of CNN further, more data augmentation techniques were needed to prevent the network from overfitting and make the network more robust against variations in the image. Additionally, importing a well-trained deep neural network used for a similar task and re-training the last few layers for the current task might increase classification accuracy as well.

  • A Compact Low-Power VLSI Architecture for Real-Time Sleep Stage Classification

    Designed sleep stage classifier algorithm for implementation in low power Actel IGLOO FPGA that controls implantable ASIC (completed in the summer of 2015)

    This project was completed in the summer of 2015 under the supervision of Professor Genov and Hossein Kassiri in the Intelligent Sensory Microsystems Laboratory. 

    A wearable-optimized implementation of a sleep stage classification algorithm that has low detection latency, high detection accuracy and low resource consumption is developed and successfully implemented on a low-power FPGA microsystem for closed-loop electrical brain stimulation. This implementation uses EEG and EMG signals as inputs and classifies stages of sleep. By structurally merging multichannel FIR and window averaging filter into one reconfigurable, multipurpose filter, the new implementation maintains a high sleep detection accuracy of 79.7% and a low detection latency of 0.982 ms, while consuming 6.8 times fewer logic elements and 96.28% less power compared with the current state of the art implementation. With its high performance and low re-source usage, this implementation enables a low-power wearable microsystem to perform neural recording, real-time REM sleep stage detection, and closed-loop responsive brain stimulation as a tool to study the mechanisms of Alzheimer’s disease.