Peter Li
Ph.D. Candidate @ MIT
Devices
Publication Types:
All types (
3 )
Biomedical (
1 )
Conference (
2 )
Devices (
1 )
Hardware (
2 )
Poster Presentation (
1 )
Robotics (
1 )
Sort by year:
Efficient Layout Techniques in TSMC 16nm FinFET using Tileable Transistors
In TSMC 16nm FinFET technology, the DRC rules are difficult to satisfy for lower level metals (M1 – M3). Furthermore, the parametric options for connecting transistor’s source or drain terminals are not available. Thus, significant time will be spent on fixing DRC violations associated with lower metal routings to transistors.