Efficient Layout Techniques in TSMC 16nm FinFET using Tileable Transistors

DevicesPoster Presentation
Peter Li, Da Kang, Qingnan Yu, Hajime Shibata
Layout Technical Conference 2017, Analog Devices
Publication year: 2017

In TSMC 16nm FinFET technology, the DRC rules are difficult to satisfy for lower level metals (M1 – M3). Furthermore, the parametric options for connecting transistor’s source or drain terminals are not available. Thus, significant time will be spent on fixing DRC violations associated with lower metal routings to transistors.